Segment 25
This sub-session began with a deep TIMELINE analysis of the Phase 8 pw=10 benchmark, which revealed that the system is perfectly GPU-bound: the measured 37.4s/proof throughput exactly matches the serial CUDA kernel time of 10 partitions × 3.75s, with cross-sector GPU transitions under 50ms and synthesis fully overlapped with GPU work, making further CPU-side optimizations unnecessary. The project documentation (cuzk-project.md) was updated with Phase 6-8 results, benchmark tables, and the TIMELINE analysis, then committed. Subsequently, the user observed GPU utilization/power dips correlating with ~50 GB/s PCIe traffic, prompting a detailed inventory of all 23.6 GiB HtoD transfers per partition inside the GPU mutex. Two root causes were identified: non-pinned host memory for a/b/c polynomials causing half-bandwidth uploads through CUDA's bounce buffer, and per-batch hard sync stalls in the Pippenger MSM where the GPU idles while the CPU processes bucket results. A two-tier mitigation plan was designed and documented in c2-optimization-proposal-9.md: Tier 1 pre-stages a/b/c outside the mutex via cudaHostRegister + async upload on a dedicated copy stream, and Tier 3 restructures the Pippenger batch loop with double-buffered host result buffers to defer syncs and eliminate GPU idle gaps between MSM batches.