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The assistant confirmed that the model is compute-bound rather than communication-bound by benchmarking TP4+PP2, which was 2× slower than TP8—ruling out allreduce latency as the primary bottleneck. A deep investigation into FP4 GEMM kernel efficiency on SM120 revealed that the GPUs only draw ~235W out of 600W TDP during inference, and the CUTLASS kernels plateau at ~1,300 TFLOPS (70% of dense peak) only for very large matrices; during actual decode, per-expert batch sizes of ~16–64 tokens achieve merely 0.8–55 TFLOPS (0.02–3% of peak). The 99KB shared memory limit on SM120 prevents using larger CUTLASS tile configurations (M128×N256 and M256×N128 fail to initialize), while cuBLASLt FP4 was found to be no faster than FlashInfer's CUTLASS path. Through systematic tuning—raising `--max-running-requests` to 2048 and setting `--num-continuous-decode-steps 8`—the assistant achieved a 28% throughput improvement at 2048 concurrency, reaching 2,095 output tok/s and 4,151 total tok/s. Multiple research agents explored expert parallelism, piecewise CUDA graphs, MSCCLPP allreduce, single-batch overlap, L2 cache pinning, persistent grouped GEMM kernels, and FP4 structured sparsity. The assistant synthesized these findings into a ranked optimization plan and began documenting each approach as `glb5improvement-xx.md` files, starting with piecewise CUDA graphs.

From Knowledge Artifact to Pipeline Parallelism: A Strategic Pivot in Blackwell Inference Optimization 3525 words

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