The Benchmark That Killed Speculative Decoding: When MTP Meets Blackwell Reality
A Single Message That Changed the Optimization Trajectory
In the high-stakes world of large language model inference on cutting-edge hardware, few moments are as decisive as a benchmark that definitively answers a major optimization question. Message <msg id=6004> in this opencode session is precisely such a moment. It contains the output of a parallel throughput benchmark run against the Qwen3.5-397B-A17B-NVFP4 model deployed on an 8× RTX PRO 6000 Blackwell GPU system, this time with NEXTN (Multi-Token Prediction / MTP) speculative decoding enabled. The results are delivered with stark numerical clarity:
C | Agg tok/s | Per-req tok/s | Tokens | Wall(s) | Ok
-----------------------------------------------------------------
1 | 172.1 | 176.1 | 4000 | 23.2 | 4
4 | 541.9 | 159.4 | 7245 | 13.4 | 8
16 | 1686.1 | 119.5 | 29567 | 17.5 | 32
32 | 2162.3 | 82.1 | 52593 | 24.3 | 64
These numbers tell a devastating story for speculative decoding on this particular hardware configuration. To understand why, we must compare them against the baseline benchmark run just minutes earlier in <msg id=5997>, which showed 172.2 tok/s at C=1 and 2156.4 tok/s at C=32 — essentially identical results. After all the effort to enable NEXTN — patching the server, fixing parameter conflicts, waiting for draft CUDA graphs to capture — the speculative decoding pathway delivered zero measurable throughput improvement.
The Context: Why This Message Was Written
This message did not emerge in a vacuum. It was the culmination of an intense, multi-session optimization campaign spanning several days of work on an 8× RTX PRO 6000 Blackwell GPU machine (architecture SM120). The assistant and user had been systematically working through a checklist of optimization strategies, and speculative decoding via the model's built-in MTP (Multi-Token Prediction) heads was one of the most anticipated items.
The reasoning behind testing NEXTN was straightforward and well-founded. The Qwen3.5-397B-A17B-NVFP4 checkpoint includes native MTP heads — additional lightweight transformer layers that predict multiple future tokens simultaneously. In theory, MTP allows the model to generate, say, 2 or 3 tokens per forward pass instead of 1, which should directly boost throughput, especially for single-request (C=1) scenarios where the GPU is underutilized waiting for sequential token generation. The user had explicitly encouraged aggressive optimization in <msg id=5979> with the directive "be aggressive - we want minimal pcie roundtrips," and NEXTN speculative decoding fit that mandate perfectly: it promised more tokens per GPU invocation without increasing PCIe communication.
The assistant invested significant effort to get NEXTN running. Message <msg id=5980> launched the first NEXTN attempt with explicit --speculative-num-draft-tokens 2 and --speculative-eagle-topk 1 flags. That crashed with an assertion error because speculative_eagle_topk must be None when spec_v2 is enabled (<msg id=5985>). A second attempt in <msg id=5983> added --mamba-scheduler-strategy extra_buffer after discovering that the hybrid GDN model required it. A third attempt in <msg id=5987> stripped the explicit draft token parameters, letting the server auto-configure. That also crashed due to a process conflict. Finally, <msg id=6001> launched the server successfully with SGLANG_ENABLE_SPEC_V2=1 and the minimal required flags, and <msg id=6002> confirmed that draft CUDA graphs had been captured successfully across all 8 GPUs. The stage was set for the benchmark that would arrive in <msg id=6004>.
The Benchmark Methodology and What It Reveals
The benchmark script (bench_qwen.py) measures aggregate throughput at multiple concurrency levels (C = 1, 4, 16, 32). Each concurrency level runs multiple requests simultaneously, measuring total tokens generated divided by wall-clock time. The "Agg tok/s" column shows the aggregate throughput across all concurrent requests, while "Per-req tok/s" shows the average per-request throughput.
At C=1 (single request), NEXTN achieved 172.1 tok/s aggregate (176.1 per-req). The baseline was 172.2 tok/s. The difference is within measurement noise — literally 0.1 tok/s. At C=4, NEXTN scored 541.9 vs baseline 542.2. At C=16, NEXTN showed a slight edge: 1686.1 vs 1646.7, a 2.4% improvement that could be attributed to variance. At C=32, the peak throughput was 2162.3 vs 2156.4 — again, indistinguishable.
The conclusion is inescapable: on this hardware configuration, NEXTN speculative decoding provides no meaningful throughput benefit at any concurrency level. The MTP heads, despite being successfully loaded and having their CUDA graphs captured, are not accelerating generation.
Why Did NEXTN Fail to Deliver?
Several hypotheses can explain this result, and the message itself does not provide the answer — it only provides the data that forces the question. The most likely explanations involve the unique characteristics of the Blackwell SM120 architecture combined with the PCIe Gen5 interconnect (no NVLink between the 8 GPUs).
First, the MTP draft model runs in BF16 (as noted in <msg id=5978>: "The MTP model is unquantized in the nvfp4 checkpoint"), while the main model runs in FP4. This means the draft model is actually slower per-token than the main model on a per-parameter basis, because FP4 throughput on Blackwell's tensor cores is substantially higher than BF16 throughput. The draft model may be small enough (presumably a few layers versus the full 397B-parameter MoE) that its overhead is minimal, but it still consumes GPU cycles that could otherwise go to the main model.
Second, on PCIe-connected GPUs, every all-reduce operation involves expensive communication over the PCIe bus. Speculative decoding introduces additional all-reduce operations for the draft model's forward passes, potentially offsetting any gains from generating multiple tokens per verification step. The user's earlier comment about minimizing PCIe roundtrips (<msg id=5979>) anticipated this exact concern.
Third, the baseline throughput was already remarkably high — 172 tok/s for a 397B-parameter MoE model on 8 GPUs is excellent. When the baseline is already well-optimized, there is less headroom for speculative decoding to improve upon. The GPU may already be nearly saturated with compute work, leaving little idle time for the draft model to fill.
Assumptions and Their Violations
The assistant made several implicit assumptions when pursuing the NEXTN path:
- MTP heads would provide a meaningful speedup. This assumption was based on published results showing MTP improving throughput by 1.5×–2× on other architectures. The Blackwell SM120 + PCIe topology proved to be a case where these gains do not materialize.
- The built-in MTP weights would be compatible with the FP4 quantized main model. While the MTP model runs in BF16 and the main model in FP4, the assistant assumed the overall pipeline would integrate cleanly. It did, functionally, but the performance didn't materialize.
- Speculative decoding would help most at low concurrency. The conventional wisdom is that speculative decoding helps single-stream throughput because it keeps the GPU busy during the sequential decode phase. At C=1, the baseline was already 172 tok/s — the GPU was apparently already well-utilized.
- The
spec_v2overlap path would reduce communication overhead. The assistant had previously pivoted tospec_v2(in segment 37) specifically because it overlaps compute with communication. Yet even with this optimization, the results were flat.
Input Knowledge Required to Understand This Message
To fully grasp the significance of <msg id=6004>, one needs to understand:
- Speculative decoding / MTP: The concept of using a smaller "draft" model to predict multiple tokens, which are then verified by the main model in a single forward pass. NEXTN is SGLang's implementation of Multi-Token Prediction using built-in model heads.
- Concurrency benchmarking: The practice of measuring throughput at different request concurrency levels to understand both single-stream latency and batch throughput. C=1 shows the best-case per-request speed, while C=32 shows the system's maximum aggregate throughput.
- The Blackwell SM120 architecture: NVIDIA's RTX PRO 6000 Blackwell GPUs have compute capability 12.0 (SM120), which requires specific kernel support. FP4 computation is a key feature, but not all backends support it on this architecture.
- PCIe vs NVLink tradeoffs: Without NVLink, all inter-GPU communication goes over PCIe Gen5, which has higher latency and lower bandwidth than NVLink. This makes communication-intensive techniques like speculative decoding less attractive.
- The optimization history: The assistant had already spent significant effort tuning FP4 backends, fixing KV cache precision, and establishing a strong baseline. This benchmark was the logical next step in a systematic optimization plan.
Output Knowledge Created
This message produces several concrete pieces of knowledge:
- NEXTN MTP provides zero throughput improvement on 8× RTX PRO 6000 Blackwell GPUs for Qwen3.5-397B-A17B-NVFP4. This is a definitive, empirically validated result.
- The baseline configuration (flashinfer_cutlass MoE + flashinfer_cudnn FP4 GEMM) is already near-optimal for this hardware. Any further optimization effort should focus on other areas, not speculative decoding.
- The benchmark methodology is sound and reproducible. The results are consistent across concurrency levels, with wall times and token counts that align with expectations.
- The optimization checklist item for NEXTN can be confidently marked as "tested — no benefit." This saves future effort that might have been spent tuning MTP parameters.
The Broader Significance
This message represents a critical decision point in the optimization campaign. The assistant had been pursuing speculative decoding as a major lever for throughput improvement, investing significant time in configuration, debugging, and testing. The flat benchmark results force a pivot: if speculative decoding cannot improve throughput, then optimization efforts must shift to other areas such as all-reduce optimization, KV cache management, or batch scheduling.
The discipline shown here is noteworthy. The assistant did not cherry-pick favorable metrics or rationalize away disappointing results. Instead, the benchmark was run cleanly, the results were presented plainly, and the data was allowed to speak for itself. This is the hallmark of rigorous engineering: forming a hypothesis, testing it, accepting the outcome, and using the new knowledge to guide the next steps.
For the reader, this message serves as a case study in the importance of empirical validation in ML systems engineering. Theoretical benefits of speculative decoding do not always translate to real-world hardware, especially when that hardware has unique characteristics like Blackwell's FP4 acceleration and PCIe-only interconnects. The only way to know is to measure — and to measure honestly.