Segment 25
The sub-session consolidated the pinned memory pool changes and then focused on improving GPU pipeline dispatch scheduling. Starting from a reactive semaphore, the assistant implemented a P-controller using a Notify-based two-phase loop, then added a dampening factor, and finally built a PI-controlled dispatch pacer that uses an exponential moving average of GPU inter-completion intervals as a feed-forward rate with PI correction on smoothed queue depth error. After deploying the pacer, the user identified that when synthesis is compute-constrained, the pacer over-dispatches and floods the system with concurrent synthesis jobs, causing CPU contention. To address this, the assistant added a synthesis throughput cap that clamps the dispatch rate to the measured synthesis completion rate with a small headroom factor, and freezes the PI integral term when the cap is active to prevent windup. The pinned memory pool fix remains deployed and effective, and the dispatch logic now incorporates both GPU and synthesis rate measurements to maintain stable, high-utilization scheduling.
The Pacer Emerges: From Semaphore to PI-Controlled Dispatch with Synthesis Throughput Cap